System-on-chip solutions

Turning your idea into reality: ASIC and FPGA made by ChipGlobe



Our objectives

  • High quality
  • Maximum performance
  • Long lifetime
  • Smallest possible design
  • All the technical requirements must be fully integrated

Our mission

  • High clock rate
  • Low energy consumption
  • High temperature tolerance


"First time right" methodology is more than just a solemn promise—it's the guiding principle behind our company. The thing that's inspired us most throughout all the years of chip development is finding the best possible way to join together, take an idea forward, and turn it into a high-end chip.

"Smaller, faster, more economical" presents a constantly growing challenge in the context of chip development technology. The journey along the way comprises every stage of the design flow as well as holistic project management.

We've been particularly stretched by demanding projects in the areas of mechanical engineering and communication technology—and we're passing this experience on to you today. This means your technological solution will contain that vital element which contributes to overall success—made by ChipGlobe.

We offer

  • RTL (Register Transfer Level) verification: Functional verification with Verilog, SystemVerilog, SystemC
  • Gate-level verification: Testing of implementation
  • RTL (Register Transfer Level) coding
  • Analog design
  • Synthesis: Mapping the circuit to the target technology with the help of constraints
  • STA (Statical Timing Analysis): Ensuring that all the constraints have been satisfied. Verification of the the timing of the design.
  • DFT (Design for Test): Production tests (scan chains, test monitoring...)
  • Formal verification: Final check to ensure that the functionality of the source list has been maintained.
  • Floor planning: Positioning of macros, memories, and IO Padring
  • Place and route: Physical positioning and wiring of all the cells in the chip
  • Power analysis: Ensuring a suitable and adequate power supply
  • Physical verification: Production test which ensures that the circuit can be manufactured in this form.
  • GDS data for mask production

What we offer

  • RTL (Register Transfer Level) verification: Functional verification with Verilog, SystemVerilog, SystemC
  • Gate-level verification: Testing of implementation
  • RTL (Register Transfer Level) coding
  • Analog design
  • Synthesis: Mapping the circuit to the target technology with the help of constraints
  • STA (Statistical Timing Analysis): Ensuring that all the constraints have been satisfied. Verification of the completed design.
  • DFT (Design for Test): Production tests (scan chains, test monitoring...)
  • Formal verification: Final check to ensure that the functionality of the source list has been maintained.
  • Floor planning: Positioning of macros, memories, and IO Padring
  • Place and route: Physical positioning and wiring of all the cells in the chip
  • Power analysis: Ensuring a suitable and adequate power supply
  • Physical verification: Production test which ensures that the circuit can be manufactured in this form.
  • GDS data for mask production