Job Fair at European Campus Rottal-Inn of Technical University Deggendorf on 5.11.2018

Report of Cooperation of Chipglobe GmbH, Infineon Technologies AG and the European Campus Rottal-Inn of the Technical University Deggendorf

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[Translate to Englisch:] Offene Positionen bei Chipglobe in Singapore

[Translate to Englisch:]

  • Design Engineers
  • Functional Verification Engineers
  • Design for Test Engineers
  • Layout and Physical Design Engineers

What we offer

  • RTL (Register Transfer Level) verification: Functional verification with Verilog, SystemVerilog, SystemC
  • Gate-level verification: Testing of implementation
  • RTL (Register Transfer Level) coding
  • Analog design
  • Synthesis: Mapping the circuit to the target technology with the help of constraints
  • STA (Statistical Timing Analysis): Ensuring that all the constraints have been satisfied. Verification of the completed design.
  • DFT (Design for Test): Production tests (scan chains, test monitoring...)
  • Formal verification: Final check to ensure that the functionality of the source list has been maintained.
  • Floor planning: Positioning of macros, memories, and IO Padring
  • Place and route: Physical positioning and wiring of all the cells in the chip
  • Power analysis: Ensuring a suitable and adequate power supply
  • Physical verification: Production test which ensures that the circuit can be manufactured in this form.
  • GDS data for mask production