[Translate to Englisch:] Nur wer das Ziel kennt, kann treffen.

The problem-solvers are coming!

Our services include:

  • Integral team management
  • Design lead functions
  • Project management
  • Verification and debugging (product test programs)
  • Test concepts for every IC (JTAG, MBist, Scan, IDDQ)
  • Certified design lead options for a variety of ASIC projects
  • Low power and multi-voltage designs
  • Comprehensive solution-finding (a procedure with the maximum problem-solving factor)

Comprehensive chip design management

"A project is only as good as it's managed."

Project success entirely depends on the people involved. We're living and working in a time when old strategies do no longer match. It's crucial how people communicate and come along with each other.

We identify with your project, as if it is our's. Managing projects as an external partner we have to demonstrate our skills and knowledge on a daily basis,  ensuring that our service is of an excellent and high quality.

We look at things "from the outside", so it's easier for us to concentrate on the essentials. Effective cooperation (a "meeting culture") is a top priority for us.
We deploy resources in a flexible and economic way to match the requirements of your project.

  • Project management
  • Synergy optimization
  • FMEA (Failure Mode Effects Analysis)
  • Resource management
  • Support and documentation

ChipGlobe World

Frontend Design

  • Cadence: JasperGold ®, Incisive ® Enterprise Simulator (HAL), Conformal ® Constraint Designer, Genus™ Synthesis (RTL Compiler), First Encounter®, Tempus™, Genus™ (RTL Compiler), Modus™ test, Conformal®, Incisive® Enterprise Simulator
  • Mentor Graphics: DFT Advisor, BSD Architect, MBISTArchitect™, LBISTArchitect™, Tessent® Testkompress®, Fastscan™, Modelsim®
  • Synopsys: SpyGlass®, SpyGlass® CDC, Design Compiler®, PrimeTime®, MSSTA (mixed signal), DFT Compiler/DFTMAX™, TetraMAX®, VCS®, TetraMAX® LBIST,
  • DFT and ATPG
  • Synthesis
  • STA (Toplevel, hier. Design, Macrolevel, mixed signal)
  • Constraining (General, DDR, SerDes Interface)
  • Formal Verification
  • VHDL and Verilog Design Expertise
  • RTL Validation and Linting
  • Low Power and Multi Voltage Designs

Backend Design

  • Ansys/Apache: ANSYS® Redhawk™
  • Cadence: Conformal® Equivalence Checker, Conformal® Low Power, First Encounter®, Innovus™ (Encounter®), Quantus™ QRC, Physical Verification System (PVS), Voltus™
  • Mentor Graphics: Calibre®,
  • Synopsys: Formality®, IC Compiler™ (ICC, ICC2), Star-RCXT™, ICV / Hercules™, Primerail
  • Physical Layout
  • Layout
  • Layout Verification
  • IR Drop Analysis
  • Low Power and Multi Voltage Designs

Functional Verification

  • Cadence: Incisive® XL, vManager™, mixed signal extention to Incisive® Enterprise Simulator, Low Power extentions
  • Mentor Graphics: Questa® verification platform products, Modelsim®
  • Synopsys: VCS® Verification Platform products
  • Languages: e, System C, C++, SystemVerilog, RNM (Real number modelling), Verilog, Verilog-AMS, VHDL
  • Constraint random coverage driven verification
  • Mixed signal metric driven verification
  • Portable Stimulus
  • Secure Designs and verification based on ISO26262

Above trademarks are owned by the respective companies in the U.S. and/or other countries